Traditionally, instruction sequences have been executed in data processing systems one at a time. In other words, in an instruction sequence a first instruction execution is completed before a next instruction executed is begun. In more modern pipeline approaches, instruction execution is divided into different phases. Therefore, multiple instructions are executed simultaneously by providing that the execution of the different phases are overlapped.
IBM Technical Disclosure Bulletin, Vol. 25, No. 1, June, 1982, pages 136-137, addresses a concept of the use of a multiple field condition register where each field is dedicated to the execution of architecturally separate instructions. This results in increased concurrency in simple condition code management.
IBM Technical Disclosure Bulletin, Vol. 29, No. 7, December, 1986, pages 3176-3177, discloses two additional fields for use in the condition register.
IBM Technical Disclosure Bulletin, Vol. 31, No. 2, July, 1988, pages 294-296, discloses a condition code register that retains the results of several arithmetic, logic or comparison operations to increase the opportunity for parallelism in operation.
It is the object of the present invention to provide an instruction dispatch apparatus that insures the proper order of instruction dispatching for execution in relationship with the setting of condition codes in a condition register.